SENIOR PD ENGINEER: SYNTHESIS & STA

<div class="elementToProof"><strong>Job Title: Senior PD engineer : Synthesis &amp; STA</strong></div> <div class="elementToProof"> </div> <div class="elementToProof"><strong>Location:</strong> Bangalore INDIA Hybrid / Remote</div> <div class="elementToProof"> </div> <div class="elementToProof"><strong>Role Overview</strong></div> <div class="elementToProof">We are seeking a highly skilled<span class="Apple-converted-space"> </span><strong>VLSI Synthesis &amp; STA Specialist</strong><span class="Apple-converted-space"> </span>to take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips.</div> <div class="elementToProof">In this role, you will act as a critical bridge between the front-end design and back-end physical implementation teams.</div> <div class="elementToProof">You will not only drive synthesis execution to meet aggressive target frequencies but also act as an advisor to the RTL team, providing structural feedback to optimize the netlist.</div> <div class="elementToProof">This role offers a distinct growth trajectory, with the expectation to expand into adjacent physical design territories, including Place and Route (PNR) and comprehensive timing convergence.</div> <div class="elementToProof"> </div> <div class="elementToProof"><strong>Key Responsibilities</strong></div> <ul> <li><strong>Synthesis Ownership:</strong><span class="Apple-converted-space"> </span>Drive and own the complete logic synthesis process for all designated blocks and sub-chips, ensuring optimal area, power, and performance metrics.</li> <li><strong>Quality Signoff:</strong><span class="Apple-converted-space"> </span>Define, execute, and monitor rigorous sanity checks to achieve a high-quality, pristine Synthesis Signoff.</li> <li><strong>RTL Collaboration:</strong><span class="Apple-converted-space"> </span>Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist prior to handoff.</li> <li><strong>Frequency &amp; LOL Optimization:</strong><span class="Apple-converted-space"> </span>Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled and aligned with high-frequency target requirements.</li> <li><strong>Micro-architecture Guidance:</strong><span class="Apple-converted-space"> </span>Go beyond reporting LOL violations; provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs to help designers transform their code into a superior, synthesis-friendly netlist.</li> <li><strong>Role Expansion:</strong><span class="Apple-converted-space"> </span>Progressively take on responsibilities in physical implementation adjacencies, actively participating in PNR execution, Static Timing Analysis (STA), and full-chip timing convergence.</li> </ul> <div class="elementToProof"><strong>Required Skills &amp; Qualifications</strong></div> <ul> <li><strong>Experience: 5 to 8 years</strong><span class="Apple-converted-space"> </span>of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.</li> <li><strong>EDA Tools Expertise:</strong><span class="Apple-converted-space"> </span>Hands-on experience with industry-standard synthesis tools, with a strong preference for<span class="Apple-converted-space"> </span><strong>Cadence Genus</strong>. Proficiency with STA signoff tools (e.g., Tempus, PrimeTime) is also required.</li> <li><strong>Timing &amp; STA:</strong><span class="Apple-converted-space"> </span>Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.</li> <li><strong>RTL &amp; Logic Fundamentals:</strong><span class="Apple-converted-space"> </span>Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.</li> <li><strong>Netlist Optimization:</strong><span class="Apple-converted-space"> </span>Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.</li> <li><strong>Scripting/Automation:</strong><span class="Apple-converted-space"> </span>Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.</li> <li><strong>Cross-Functional Communication:</strong><span class="Apple-converted-space"> </span>Excellent analytical and communication skills to effectively negotiate solutions between RTL and Physical Design teams.</li> </ul> <div class="elementToProof"><strong>Preferred Qualifications</strong></div> <ul> <li>Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2) and a solid understanding of how synthesis decisions impact physical placement and routing congestion.</li> <li>Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).</li> <li> <div>Knowledge of advanced technology nodes (e.g., 5nm, 3nm) and their specific synthesis/timing challenges.</div> </li> </ul>